1. Technical Field
The present disclosure relates to a semiconductor device and, more particularly, to a method of fabricating a semiconductor device having multiple gate dielectric layers and a semiconductor device fabricated thereby.
2. Discussion of Related Art
As semiconductor devices are applied for use in various fields, device characteristics required for specific products also cover a wide range. To meet such demands, the necessity of a system-on-chip (SOC) where a memory and a logic circuit are incorporated in one chip has been recently increasing. Representative examples of the chip may include a Merged DRAM & Logic (MDL) device where a DRAM region and a logic region are merged, and a Merged Flash & Logic (MFL) device, where a flash memory region and a logic region are merged.
It is necessary to form a gate dielectric layer having various thicknesses in order to form devices having different operating voltages within a single chip. For example, in the case of an MDL device, a relatively thick gate dielectric layer should be formed because a high voltage is applied to the gate dielectric layer in the DRAM region, whereas a relatively thin gate dielectric layer should be formed in the logic region where a fast operating speed is required. In addition, a gate dielectric layer having various thicknesses is required to have different operating voltages even in a chip composed of the same kind of devices. Accordingly, various techniques for forming dual gate dielectric layers or multiple gate dielectric layers that have different thicknesses on a In semiconductor substrate have been researched. For example, a method of forming multiple gate dielectric layers is disclosed in U.S. Pat. No. 6,403,425 B1 entitled “Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide.”
FIGS. 1A to 1D are cross-sectional views illustrating a method of fabricating a conventional semiconductor device having multiple gate dielectric layers. Referring to FIGS. 1A to 1D, reference symbol “H” denotes a high-voltage MOS transistor region, and reference symbol “L” denotes a low-voltage MOS transistor region.
Referring to FIG. 1A, a pad oxide layer 5 and a hard mask 10 may be sequentially stacked on a first active region 3a in a high-voltage MOS transistor region H of a semiconductor substrate 1 and on a second active region 3b in the low-voltage MOS transistor region L of the semiconductor substrate 1. The pad oxide layer 5 may be formed of a thermal oxide layer, and the hard mask 10 may be formed of a silicon nitride layer.
The semiconductor substrate 1 may be etched using the hard mask 10 as an etch mask to form a trench 15. Subsequently, an isolation layer 20 filling the trench 15 may be formed. The isolation layer 20 may be formed of a silicon oxide layer by a chemical vapor deposition (CVD) method.
Referring to FIG. 1B, the hard mask (10 of FIG. 1A) may be removed. Subsequently, the pad oxide layer (5 of FIG. 1A) may be removed. The pad oxide layer (5 of FIG. 1A) may be etched by a wet etching process to expose the first active region 3a and the second active region 3b. The pad oxide layer (5 of FIG. 1A), however, is a thermal oxide layer, and the isolation layer 20 is a silicon oxide layer formed by CVD, so that the isolation layer 20 can be etched faster than the pad oxide layer (5 of FIG. 1A). As a result, first recessed regions D1, that is, dent regions, are formed in upper edge regions of the isolation layers 20.
Subsequently, the semiconductor substrate having the first recessed regions D1 is thermally oxidized to form a first gate oxide layer 25 on each of the exposed first and second active regions 3a and 3b. The first gate oxide layers 25 remain while subsequent processes are carried out, and act as a gate dielectric layer of a high-voltage MOS transistor. As the thickness of the first gate oxide layer 25 increases during the thermal oxidation, the thickness of the portion of first gate oxide layer 25 on the upper corner of the first active region 3a becomes relatively smaller. Such a phenomenon is referred to as a thinning effect.
Referring to FIG. 1C, a photoresist pattern 30 having an opening exposing the low-voltage MOS transistor region L may be formed on the substrate having the first gate oxide layers 25. The first gate oxide layer 25 in the low-voltage MOS transistor region L is then wet-etched using the photoresist pattern 30 as an etch mask to expose the second active region 3b. As a result, second recessed regions D2 deeper than the first recessed regions D1 are formed in edge regions of the isolation layer 20 in the low-voltage MOS transistor region L.
Referring to FIG. 1D, the photoresist pattern 30 may be removed in the high-voltage MOS transistor region H. The semiconductor substrate having the second recessed regions D2 is then thermally oxidized to form a second gate oxide layer 35 that is thinner than the first gate oxide layer 25 on the second active region 3b. In this case, the first gate oxide layer 25 on the first active region 3a is barely grown. Accordingly, the first gate oxide layer 25 has almost the same thickness as its initial thickness. But even so, the first recessed regions D1 still remain in the edge regions of the isolation layer 20 in the high-voltage MOS transistor region H, and the second recessed regions D2 deeper than the first recessed regions D1 remain in the edge regions of the isolation layer 20 in the low-voltage MOS transistor region L.
A gate conductive layer is formed on the entire surface of the semiconductor substrate having the second gate oxide layer 35. The gate conductive layer is patterned to form a high-voltage gate electrode 40a crossing over the first active region 3a and a low-voltage gate electrode 40b crossing over the second active region 3b. Consequently, the first gate oxide layer 25 acts as a gate dielectric layer of the high-voltage MOS transistor, and the second gate oxide layer 35 acts as a gate dielectric layer of the low-voltage MOS transistor.
According to the conventional art as described above, the first recessed regions D1 are formed in the edge regions of the isolation layer in the high-voltage MOS transistor region, and the second recessed regions D2 deeper than the first recessed regions D1 are formed in the edge regions of the isolation layer in the low-voltage MOS transistor region. Accordingly, the subthreshold characteristics of the high-voltage MOS transistor, as well as the subthreshold characteristics of the low-voltage MOS transistor, are significantly deteriorated.
Because the thickness of the first gate dielectric layer 25 covering the edge corner of the first active region 3a is relatively smaller than the thickness of the first gate dielectric layer 25 formed on a center portion of the first active region 3a, a breakdown voltage of the gate dielectric layer of the high-voltage MOS transistor significantly decreases. Consequently, the reliability of the high-voltage MOS transistor is deteriorated. In addition, the second recessed regions D2 may expose upper sidewalls of the second active region 3b. As a result, the thickness of the second gate dielectric layer 35 covering the upper edge corner of the second active region 3b is relatively smaller than the thickness of the second gate dielectric layer 35 formed on a center portion of the second active region 3b. Accordingly, the MOS transistor may be turned on at a voltage lower than a threshold voltage, that is, a reverse narrow width effect may occur.